The present invention relates to an integrated circuit with multi-stage frequency-dividing circuits. The integrated circuits according to the present invention can be used, for example, for driving analog type electronic clocks or watches.
FIG. 1 illustrates a conventional circuit for driving an analog type electronic clock. The 4.194304 MHz output of a quartz oscillator 11 is fed to a frequency-dividing circuit 12' which consists of 23 flip-flop circuits. The frequency-dividing circuit 12' divides the frequency by 2.sup.23, and produces a set of pulse trains having a frequency of 0.5 Hz and phases which are shifted by 1/2 period. The pulse trains are fed to a pulse processing circuit 2 which produces an output for a motor drive circuit 5. The outputs of the motor drive circuit are fed from output terminals 8a, 8b to a step motor for driving the second hand, and to a time warning device (alarm) from an output terminal 7 via an output buffer 3. A reset signal for setting the time is fed to a reset terminal 6.
FIG. 2 illustrates signal waveforms obtained at the output terminals 8a, 8b of the motor drive circuit of FIG. 1. Namely, the output pulse produced at the terminal 8a and the output pulse produced at the terminal 8b have a period of 2 seconds, i.e., have a frequency of 0.5 Hz, and further have phases which are shifted by 1/2 cycle relative to each other. Therefore, the motor performs one step motion per one second. The reset operation in the circuit of FIG. 1 is not effected (RST) when the output pulses at the terminals 8a, 8b are of the high level, but is effected (RST) when the output pulses are of the low level. Further, in order for the motor to reliably operate after the reset has been effected, a pulse from the terminal opposite to that of the pulse that was fed at the time of effecting the reset is fed to the motor after the reset has been effected. That is, when the reset is effected after a pulse on the side 8a has been generated, a pulse on the side 8b is fed after the reset is completed. When the reset is effected after a pulse on the side 8b has been generated, a pulse on the side 8a is fed after the reset is completed. Here, the circuit of FIG. 1 is housed in a package having 8 pins, or leads. Among the 8 pins, 2 pins are used for the power supply, 2 pins are used for connection to the quartz crystal, 2 pins are used for driving the motor, 1 pin is used for effecting the resetting, and 1 pin is used for driving the alarm. Therefore, there are no extra pins.
In order to test the circuit of FIG. 1, one might consider using input terminals for introducing test signals, and feeding high-frequency test pulses through such terminals in order to effect the test within a short period of time. As mentioned above, however, there are no extra pins available for use as test terminals. Accordingly, a test utilizing the test signal input terminals cannot be conducted.